Speed Enhancement with Soft Computing Hardware

During the past few years JPL has been actively involved in soft computing research encompassing theory, architecture, and electronic hardware applications. There are a host of soft computing applications that require orders of magnitude enhancement in speed compared to that obtained using simulations on digital machines. For on-board computing this is made possible by selecting suitable algorithms, designing compatible architectures and implementing them in parallel processing hardware. Compact low-power hardware designs include neural network multi-chip module performing high-speed object classification and recognition with 10” multiply-sum operations per second (ops). Additionally, development on evolvable hardware implemented on suitable electronic hardware has shown exciting high-speed evolution of various digital and analog circuits. We will review our work on electronic neural networks and evolvable hardware to bring out speed advantage.